Fairylog

Written by Ross McKinlay

Fairylog, a Verilog dialect powered by the Racket meta fairies.

A source-to-source Verilog compiler, with a number of nice compile time features. Full Racket integration, providing macros and compile time programming for FPGA projects.

1 Fairylog Overview

1 Fairylog Overview

TODO

This project in its early experimental stage and is in constant flux.